Senior Chiplet Validation & Test Engineer

TylSemi, Inc.; San Jose (CA); On-site; USD 180,000 - 216,000; Full time

Job summary

TylSemi, Inc. San Jose, California, United States seeks an experienced Senior Development Test Engineer to own end-to-end testing, characterization and failure analysis of next-generation multi-die packages.

You will lead validation across high-speed die-to-die interconnects (UCIe), PDN/PMIC, PMC, PCIe/CXL subsystems, applying statistics and ML to test data while ensuring traceability from requirements to evidence. This role demands deep hardware test expertise and fast decision-making.

Qualifications

• 8–10+ years in post-silicon validation or complex SoCs/ASICs.
• Experience with multiple die packages and PCIe/CXL/UCIe interconnects.
• Strong hardware test and measurement skills with lab equipment.
• Ability to translate requirements into validation evidence.

Responsibilities

• Own end-to-end testing strategy for multi-die packages.
• Develop test content in C and Python for bare-metal and drivers.
• Build scalable test automation with HIL and CI/CD.
• Perform bench-to-ATE handoffs and validation across PDN/PMIC/PMC.
• Apply statistical analysis and ML to test data for root-cause insights.

Skills

Post-silicon validation

C & Python test content

Lab instrumentation

High-speed protocols (PCIe/CXL/UCIe)

Fault injection

Automation frameworks

Education

BS or MS in Electrical/Computer Engineering

Tools

Git

CMake

GCC/Clang

CI pipelines

Job description

TylSemi, Inc. San Jose, California, United States seeks an experienced Senior Development Test Engineer to own end-to-end testing, characterization and failure analysis of next-generation multi-die packages.

You will lead validation across high-speed die-to-die interconnects (UCIe), PDN/PMIC, PMC, PCIe/CXL subsystems, applying statistics and ML to test data while ensuring traceability from requirements to evidence. This role demands deep hardware test expertise and fast decision-making.