Lead High-Speed IO Architect for PCIe/UCIe & Ethernet

TylSemi, Inc.; San Jose (CA); On-site; USD 175,000 - 350,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA seeks a High-Speed IO Architect to own the PCIe/UCIe/Ethernet interface architecture and drive tape-out readiness across multi-die chiplet platforms.

You will define die-to-die integration, serdes-to-photonics interfaces, and SI budgets while collaborating with digital/analog teams and anchor customers to align product definitions with platform requirements.

Qualifications

• 15+ years in high-speed interface architecture.
• 5+ years at Principal level or higher in fabless or IDM.
• PCIe architecture across PHY, controller and protocol stacks.
• UCIe familiarity with die-to-die integration.
• S-parameter analysis and channel simulation (HSPICE/IBIS-AMI).
• Experience with CoWoS/EMIB/InFO packaging.
• Track record delivering complex IP integrations to tape-out.
• Startup experience and comfort with ambiguity.

Responsibilities

• Define high-speed IO architecture across PCIe and Ethernet scale-up fabric.
• Define die-to-die interface architecture for UCIe integration.
• Architect SerDes-to-photonics interface and co-packaged optics readiness.
• Own the signal integrity budget: TX/RX equalization and margins.
• Guide SerDes PHY selection and vendor IP integration.
• Define UCIe PHY integration, power domains and pad ring architecture.
• Collaborate on protocol bridge design: PCIe TLP to UCIe conversion.
• Drive DFT and compliance test architecture for PCIe/UCIe conformance.
• Establish PVT margins and per-lane DVFS/IVR coordination.
• Engage anchor customers to validate requirements (AWS/Google/Microsoft/Meta).
• Roadmap IP reuse and identify patentable innovations.

Skills

High-speed IO

PCIe architecture

UCIe familiarity

Signal integrity

Tape-out experience

Advanced packaging

IP integration leadership

Multi-die architectures

SerDes optics

Startup experience

Job description

TylSemi, Inc. in San Jose, CA seeks a High-Speed IO Architect to own the PCIe/UCIe/Ethernet interface architecture and drive tape-out readiness across multi-die chiplet platforms.

You will define die-to-die integration, serdes-to-photonics interfaces, and SI budgets while collaborating with digital/analog teams and anchor customers to align product definitions with platform requirements.