A leading technology company is seeking a Senior Cell Modeling and Verification Engineer to develop behavioral models and verification for mixed signal design cells used in ASIC products. This role requires significant experience with Verilog HDL, RTL simulation, and collaboration with cross-functional teams. Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering and have at least 3 years of relevant experience. The position offers a hybrid work environment with a competitive salary range of $136,000 to $218,500.
Qualifications
3+ years of relevant experience.
Hands-on experience with RTL simulation and waveform debug.
Strong understanding of Verilog HDL.
Responsibilities
Develop behavioral models and verification for mixed signal design cells.
Collaborate with cross-functional teams for library build and ASIC verification.
Document and deliver high performance RTL.
Skills
RTL simulation
Verilog HDL
Python
Perl
digital design concepts
Education
Bachelors or Masters in Electrical Engineering or Computer Engineering
Job description
A leading technology company is seeking a Senior Cell Modeling and Verification Engineer to develop behavioral models and verification for mixed signal design cells used in ASIC products. This role requires significant experience with Verilog HDL, RTL simulation, and collaboration with cross-functional teams. Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering and have at least 3 years of relevant experience. The position offers a hybrid work environment with a competitive salary range of $136,000 to $218,500.