Senior Cell Modeling and Verification Engineer

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 218,500; Full time

Job summary

NVIDIA Gruppe is seeking a Senior Cell Modeling and Verification Engineer in Santa Clara, CA, to develop ASIC products and ensure design quality. Candidates should have experience in circuit and digital design, Verilog, SystemVerilog, and scripting languages.

The role requires collaboration within cross-functional teams, delivering high-performance RTL models for NVIDIA's innovative technologies. The position offers a competitive salary range of 136,000 USD - 218,500 USD and eligibility for equity and benefits.

Qualifications

• 3+ years of relevant experience.
• Hands-on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.

Responsibilities

• Develop behavioral model and verification for custom mixed signal design cells.
• Collaborate with cross-functional teams on library build and ASIC verification.
• Document and deliver high-performance RTL.

Skills

Verilog HDL

Scripting (Python, Perl)

RTL simulation

Digital design concepts

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Job description

The NVIDIA VLSI team is looking for a Senior Cell Modeling and Verification Engineer with strong experience in hardware design and methodologies to help develop NVIDIA's ground breaking ASIC products and work hands on with new NVIDIA hardware to ensure it meets design, feature, and quality objectives. This role is at the intersection of circuit design and digital design to help craft the most power-efficient and performance leading SoCs and GPUs.

Responsibilities

• Work with sophisticated technologies and develop behavioral model and verification for custom mixed signal design cells that would be used on all the NVIDIA products.
• Use Verilog, SystemVerilog, Perl, or Python and understanding of PLL and other high-speed interconnects to model, verify, emulate/prototype mixed-signal designs.
• Collaborate with cross function teams with regards to library build, cell integration, ASIC verification and DFT simulation.
• Document, implement, and deliver fully verified and high performance RTL to achieve design targets.

Qualifications

• Bachelor's or Master's in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of relevant experience.
• Hands-on experience with RTL simulation and waveform debug.
• Strong understanding of Verilog HDL.
• Scripting experience and skills using Python or Perl.
• Knowledge of fundamental digital design and logic design concepts.

Preferred Experience

• Previous digital design experience.
• Previous experience running simulations in Verilog.
• Ability to collaborate with many groups and communicate technical details.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until May 24, 2026.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.