Performance Modeling Architect - Cache & NoC Innovations

NVIDIA Corporation

Santa Clara (CA)

On-site

USD 184,000 - 288,000

Full time

14 days+
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Job summary

NVIDIA Corporation in Santa Clara is seeking a Performance Modeling Architect to define and improve CPU cache hierarchies and interconnects for automotive and data center systems.

You will develop cycle-accurate performance models (C++/SystemC), analyze bottlenecks, and evaluate coherency protocols. Collaboration with software and verification teams will optimize drivers and validate models against silicon.

Qualifications

  • Master’s or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent) with 5+ years of experience.
  • Strong understanding of CPU microarchitecture, memory consistency models, and cache coherency protocols.
  • Proven experience in C++ or SystemC for cycle-accurate or functional modeling.
  • Proficiency in Python or similar scripting languages for data processing and visualization.
  • Understanding of NoC topologies (Mesh, Ring, Torus) and arbitration logic.

Responsibilities

  • Develop and maintain high-fidelity, cycle-accurate performance models for coherent interconnects and large-scale caches.
  • Model and analyze performance bottlenecks across automotive and data center scales.
  • Evaluate performance impact of coherency protocols and snooping filters.
  • Run industry benchmarks to drive architectural trade-offs and optimize drivers.

Skills

CPU microarchitecture
Memory coherency
C++/SystemC
Python scripting
NoC topologies

Education

Master's or PhD in relevant field

Tools

C++
SystemC

Job description

NVIDIA Corporation in Santa Clara is seeking a Performance Modeling Architect to define and improve CPU cache hierarchies and interconnects for automotive and data center systems.

You will develop cycle-accurate performance models (C++/SystemC), analyze bottlenecks, and evaluate coherency protocols. Collaboration with software and verification teams will optimize drivers and validate models against silicon.

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