Senior ASIC Verification Lead - SystemVerilog/UVM

Teradyne; Reading (MA); Hybrid; USD 155.000 - 308.000; Vollzeit

Benefits dieser Stelle

Discretionary bonus eligibility

Comprehensive benefits

Salary range competitiveness

Zusammenfassung

Teradyne is seeking a Sr. ASIC Verification Engineer in North Reading, MA to lead verification planning and develop advanced verification environments for complex ASIC/SoC designs.

You will collaborate with design, firmware, software, and validation teams to ensure comprehensive coverage and high-quality outcomes. The role requires 8+ years in ASIC/SoC verification, strong SystemC, C++, SystemVerilog/UVM experience, and knowledge of functional verification methodologies.

Qualifikationen

• 8+ years of ASIC/SoC verification experience in semiconductor product development.
• Strong experience with SystemC and C++.
• Strong Object Oriented Programming experience.
• Strong experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting using Python, Perl, or similar languages.
• Knowledge of industry-standard EDA simulation and debug tools.

Aufgaben

• Lead verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Mentor junior engineers on verification methodologies, coding practices, and debugging techniques.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

Kenntnisse

SystemC

C++

Object Oriented Programming

SystemVerilog

UVM

Python

Perl

Communication

Ausbildung

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree preferred

Tools

EDA tools

Jobbeschreibung

Teradyne is seeking a Sr. ASIC Verification Engineer in North Reading, MA to lead verification planning and develop advanced verification environments for complex ASIC/SoC designs.

You will collaborate with design, firmware, software, and validation teams to ensure comprehensive coverage and high-quality outcomes. The role requires 8+ years in ASIC/SoC verification, strong SystemC, C++, SystemVerilog/UVM experience, and knowledge of functional verification methodologies.