Senior ASIC Verification Engineer

Insight Global; North Reading (MA); On-site; USD 140,000 - 180,000; Full time

Job summary

Insight Global is seeking a Senior ASIC Verification Engineer in North Reading, MA to drive architecture-level modeling and verification of complex ASIC/SoC designs using SystemC and C++. The role emphasizes reference-model development and validation against architectural specs, not just testbench work.

You will collaborate with architecture, design, and verification teams, build scalable modeling frameworks, and contribute to verification methodologies.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or Computer Science required.
• 8+ years in ASIC or SoC verification in semiconductor product development.
• Strong OO programming with SystemC and/or C++.
• Experience with SystemVerilog and UVM verification environments.
• Deep knowledge of ASIC architecture, RTL verification, and debugging.

Responsibilities

• Develop and maintain SystemC and C++ reference models for ASIC/SoC verification.
• Collaborate with architecture, design, and verification teams across the product lifecycle.
• Validate RTL implementations against architectural specs and reference models.
• Investigate and debug discrepancies between specifications, models, and RTL designs.
• Design scalable, reusable modeling frameworks and verification infrastructure.
• Translate architecture requirements into accurate behavioral models.
• Drive verification strategy at architecture and subsystem levels.
• Contribute to methodology improvements and best practices.

Skills

SystemC

C++

SystemVerilog

UVM

ASIC/SoC verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

We are seeking a Senior ASIC Verification Engineer to join a cutting-edge semiconductor organization in North Reading, MA. This role is ideal for an engineer with a strong software development mindset who is passionate about ASIC architecture, modeling, and verification at the system level.

Unlike traditional Design Verification positions focused primarily on UVM testbench development and coverage closure, this role centers on developing and maintaining reference models used to validate complex ASIC and SoC designs. The ideal candidate will have deep expertise in SystemC, C++, object-oriented programming, and architecture-level modeling.

What You'll Do

• Develop and maintain SystemC and C++ reference models used for ASIC/SoC verification.
• Collaborate closely with architecture, design, and verification teams throughout the product development lifecycle.
• Validate RTL implementations against architectural specifications and reference models.
• Investigate and debug discrepancies between specifications, reference models, and RTL designs.
• Design scalable, reusable modeling frameworks and verification infrastructure.
• Review architecture requirements and translate them into accurate behavioral models.
• Drive verification strategy at the architecture and subsystem levels.
• Contribute to methodology improvements and best practices across verification and modeling teams.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (preferred).
• 8+ years of ASIC or SoC verification experience within semiconductor product development.
• Strong object-oriented programming experience using SystemC and/or C++.
• Experience developing verification environments utilizing SystemVerilog and UVM.
• Deep understanding of ASIC architecture, digital design, and RTL verification methodologies.
• Strong debugging and problem-solving skills with the ability to identify root causes across models, specifications, and RTL implementations.