Senior ASIC Verification Lead - RTL, UVM, Debug & Mentoring

Retym; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Retym, a well-funded startup in Austin, seeks a Senior Verification Engineer to drive RTL verification across multiple design aspects. You will own end-to-end block verification from scratch, shape test bench architecture, define test plans and coverage, and collaborate with design, architecture and algo teams.

You will mentor junior engineers, perform coverage analysis, debug with design teams, and ensure verification milestones align with the design schedule.

Qualifications

• 5+ years of experience in verification
• 2+ full block/system verification cycles
• In-depth knowledge of VLSI verification flow, languages and concepts
• Experience in data path or data protocols, Ethernet preferred
• Verification using methodologies such as UVM or eRM

Responsibilities

• Plan and perform verification of digital design blocks according to the design specification and interact with design engineers
• Build verification environments using SystemVerilog and UVM
• Identify and write coverage measures for corner-cases
• Debug functionality with design engineers
• Perform coverage collection and close the full functionality using metrices

Skills

SystemVerilog

UVM

VLSI verification

Test bench architecture

Ethernet verification

Mentoring

Tools

UVM

eRM

SystemVerilog

Job description

Retym, a well-funded startup in Austin, seeks a Senior Verification Engineer to drive RTL verification across multiple design aspects. You will own end-to-end block verification from scratch, shape test bench architecture, define test plans and coverage, and collaborate with design, architecture and algo teams.

You will mentor junior engineers, perform coverage analysis, debug with design teams, and ensure verification milestones align with the design schedule.