Senior ASIC Verification Engineer - RTL, UVM, AI-Driven

Upscale AI; Northern (KY); Hybrid; USD 212,000 - 246,000; Full time

Job summary

Upscale AI in the United States is seeking a senior ASIC verification engineer with 10+ years of industry experience (or a master’s with 7+ years) to design, verify, and maintain block- and system-level verification environments and testbenches for high-performance AI ASICs.

You will drive verification planning, coverage, ABV, and formal methods, collaborating with design teams to accelerate development cycles and improve quality.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of industry experience.
• Or a Master's degree with 7+ years of relevant experience.
• Proven experience verifying complex ASIC designs at block and system levels.

Responsibilities

• Design, develop, and maintain verification environments, testbenches, and reference models for block- and system-level designs.
• Develop verification plans and test cases to ensure complete functional coverage.
• Verify RTL designs using directed testing, constrained-random verification, ABV, formal verification, and functional coverage.
• Perform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations.
• Debug and resolve design and verification issues with cross-functional teams.
• Drive adoption of advanced verification methodologies and automation frameworks.
• Apply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, and coverage.

Skills

SystemVerilog

UVM

ASIC verification

C/C++/Python

Debugging

Regression management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree in related field (optional)

Job description

Upscale AI in the United States is seeking a senior ASIC verification engineer with 10+ years of industry experience (or a master’s with 7+ years) to design, verify, and maintain block- and system-level verification environments and testbenches for high-performance AI ASICs.

You will drive verification planning, coverage, ABV, and formal methods, collaborating with design teams to accelerate development cycles and improve quality.