Senior ASIC Verification Engineer - UVM/SystemVerilog

Snap Inc.; United States; On-site; USD 147,000 - 259,000; Full time

Benefits offered by this job

Paid parental leave

Comprehensive medical coverage

Mental health support programs

Equity in the form of RSUs

Job summary

A leading technology company in the United States is looking for an experienced individual to design display Integrated Circuits for Augmented Reality. This role involves collaboration with engineers from various disciplines and requires strong verification skills in ASIC Design. The ideal candidate will have over 10 years of experience, a BSEE or MSEE, and expertise in UVM and Siemens Questa. Competitive salary ranges from $147,000 to $259,000 annually with full benefits, including equity options.

Qualifications

• 10+ years of experience in ASIC Design Verification.
• Strong knowledge of UVM and SystemVerilog.

Responsibilities

• Designing display Integrated Circuits for AR.
• Developing and implementing verification test plans.

Skills

UVM

SystemVerilog

Siemens Questa

Verilog RTL coding practices

Scripting

Linux environment

English communication

Education

BSEE or MSEE or relevant experience

Job description

A leading technology company in the United States is looking for an experienced individual to design display Integrated Circuits for Augmented Reality. This role involves collaboration with engineers from various disciplines and requires strong verification skills in ASIC Design. The ideal candidate will have over 10 years of experience, a BSEE or MSEE, and expertise in UVM and Siemens Questa. Competitive salary ranges from $147,000 to $259,000 annually with full benefits, including equity options.