ASIC Verification Engineer — First‑Pass Silicon & Equity

Broadcom

Fort Collins (CO)

On-site

USD 110,000 - 176,000

Full time

37 hours ago
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Benefits offered by this job

Discretionary annual bonus
New hire equity grant
Annual equity awards
401(k) matching
Employee Stock Purchase Program (ESPP)
Paid holidays
Paid sick leave
Paid vacation

Job summary

Broadcom is seeking an ASIC Verification Engineer in Fort Collins, Colorado to design, implement, and maintain verification infrastructure for a diverse ASIC portfolio. In this role, you will collaborate with design teams to develop exhaustive verification plans, construct reusable testbenches, and continuously scale verification coverage to ensure first-pass silicon success.

Key responsibilities include building testbenches with SystemVerilog/UVM, writing coverage-driven tests, and maintaining

Qualifications

  • Bachelor's or Master’s degree with required years of ASIC verification experience as specified in the ad.

Responsibilities

  • Design and implement verification environments using SystemVerilog and UVM.
  • Create reusable components including reference models, checkers, monitors, scoreboards and firmware code.
  • Develop verification plans, run constrained-random tests, and debug complex ASIC IP blocks.
  • Manage regression runs, triage failures and track coverage and QA.

Skills

SystemVerilog
UVM
Verilog
SVA
C/C++
Python scripting
ARM architecture
AMBA AXI/ABP
DSP reference models

Education

Bachelor's degree in Electrical/Computer Engineering or related field
Master's degree in related field

Job description

Broadcom is seeking an ASIC Verification Engineer in Fort Collins, Colorado to design, implement, and maintain verification infrastructure for a diverse ASIC portfolio. In this role, you will collaborate with design teams to develop exhaustive verification plans, construct reusable testbenches, and continuously scale verification coverage to ensure first-pass silicon success.

Key responsibilities include building testbenches with SystemVerilog/UVM, writing coverage-driven tests, and maintaining

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