Senior ASIC Verification Engineer — Tapeouts & UVM

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants & annual equity awards

401(k) matching

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom in San Jose, CA seeks an experienced ASIC verification engineer to join the system-level verification team. You will develop complex verification environments, build test plans, and verify high‑performance network switch ASICs/SoCs across ASIC/FPGA implementations.

The ideal candidate has 8+ years in ASIC design/verification, strong Verilog and C/C++, UVM/SystemVerilog, and a track record of multiple tape-outs from concept to production; excellent English communication across

Qualifications

• Experience: 8+ years of ASIC design/verification experience, including a complete understanding of Verilog design and hands‑on experience with C/C++.
• Education: Bachelor's in Engineering
• Methodologies & Languages: Strong working knowledge of object-oriented programming (OOP) and modern ASIC verification flows (e.g., UVM/SystemVerilog).
• Technical Depth: Complete mastery of Verilog for simulation and familiarity with ASIC design flows for deep sub‑micron technologies.
• Domain Knowledge: Experience with networking protocols (e.g., Ethernet, PCIe, routing/switching) is a major plus.
• Track Record: Must have completed multiple ASIC tape‑outs, with at least one project taken from initial concept through full production.
• Communication: Fully comfortable with technical and business English across documentation, cross‑functional collaboration, and executive communications.

Responsibilities

• Develop complex verification environments for ASICs.
• Create comprehensive test plans and scenarios.
• Verify high-performance network switch ASIC/FPGA.
• Collaborate with system architects, design engineers, and verification teams.
• Lead testbenches from concept to production across multiple tape-outs.

Skills

Verilog design/verification

C/C++

UVM

SystemVerilog

Networking protocols

Tape-out experience

Business English communication

Cross-functional collaboration

Education

Bachelor's in Engineering

Job description

Broadcom in San Jose, CA seeks an experienced ASIC verification engineer to join the system-level verification team. You will develop complex verification environments, build test plans, and verify high‑performance network switch ASICs/SoCs across ASIC/FPGA implementations.

The ideal candidate has 8+ years in ASIC design/verification, strong Verilog and C/C++, UVM/SystemVerilog, and a track record of multiple tape-outs from concept to production; excellent English communication across