Senior ASIC Verification Engineer SystemVerilog/UVM & Power IP

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive salary

Discretionary bonus program

Annual RSU grants

Comprehensive benefits package

Job summary

A leading technology firm is seeking an experienced engineer in San Diego to manage the complete verification lifecycle for digital power IPs. The ideal candidate has a Bachelor's degree in Engineering or Science and over four years of experience in ASIC design and verification, with proficiency in SystemVerilog and related methodologies. This role offers a competitive salary and dynamic work environment.

Qualifications

• Bachelor's degree in a related field and 4+ years in ASIC design.
• Master's degree and 3+ years or PhD and 2+ years in ASIC work.
• Experience with scripting/automation skills.

Responsibilities

• Manage complete verification lifecycle for digital power IPs.
• Develop testbench using SystemVerilog-UVM and perform coverage development.
• Implement power-aware UPF verification methodology.

Skills

ASIC design and verification methodology

SystemVerilog

Automation scripting

Digital design concepts

C/C++ programming

Education

Bachelor's degree in Engineering, Science, or related field

Master's degree in Computer Science, Electrical Engineering, or related field

Tools

SystemVerilog-UVM

Verification methodologies (UVM, OVM)

Perl

Python

Job description

A leading technology firm is seeking an experienced engineer in San Diego to manage the complete verification lifecycle for digital power IPs. The ideal candidate has a Bachelor's degree in Engineering or Science and over four years of experience in ASIC design and verification, with proficiency in SystemVerilog and related methodologies. This role offers a competitive salary and dynamic work environment.