Senior ASIC Verification Engineer — RTL/UVM, SystemVerilog

Technical-Link N. America; Minnesota; On-site; USD 120,000 - 180,000; Full time

Job summary

Technical-Link N. America seeks an experienced ASIC Design Verification Engineer to own the full chip development lifecycle from architecture through production release.

The candidate will verify circuits, logic and systems using UVM and SystemVerilog, and will advise on best verification methods for the digital system before silicon. Ideal candidates have RTL experience and knowledge of EDA tools.

Qualifications

• Experience developing UVM testbenches for verifying ASIC digital designs from scratch.
• Ability to review target specifications for completeness and feasibility.
• Develop test plans and specifications for complex SOC blocks.
• Verifying complex digital designs using reusable RTL methods (Verilog, SystemVerilog, UVM).
• Experience with modern verification methods and coverage metrics.

Responsibilities

• Develop UVM testbenches to verify ASIC digital designs from scratch.
• Review and edit target specifications for completeness.
• Develop test plans and specifications for complex SOC blocks.
• Verify complex digital designs using RTL methods (Verilog, SystemVerilog, UVM).
• Collaborate on verification plans and coverage metrics.
• Support DFT, test hooks, and production test planning.

Skills

UVM

SystemVerilog

Verilog

VHDL

RTL design

EDA tools

VCS-MX

Verdi

Questa

UPF

Education

Bachelor's/Master's in Electronic Engineering or Computer Science

Tools

Synopsys VCS-MX

Mentor Questa

Synopsys Formality

Mentor Calibre

Job description

Technical-Link N. America seeks an experienced ASIC Design Verification Engineer to own the full chip development lifecycle from architecture through production release.

The candidate will verify circuits, logic and systems using UVM and SystemVerilog, and will advise on best verification methods for the digital system before silicon. Ideal candidates have RTL experience and knowledge of EDA tools.