Application Specific Integrated Circuit Verification Engineer

Technical-Link N. America; Minnesota; On-site; USD 120,000 - 180,000; Full time

Job summary

Technical-Link N. America seeks an experienced ASIC Design Verification Engineer to own the full chip development lifecycle from architecture through production release.

The candidate will verify circuits, logic and systems using UVM and SystemVerilog, and will advise on best verification methods for the digital system before silicon. Ideal candidates have RTL experience and knowledge of EDA tools.

Qualifications

• Experience developing UVM testbenches for verifying ASIC digital designs from scratch.
• Ability to review target specifications for completeness and feasibility.
• Develop test plans and specifications for complex SOC blocks.
• Verifying complex digital designs using reusable RTL methods (Verilog, SystemVerilog, UVM).
• Experience with modern verification methods and coverage metrics.

Responsibilities

• Develop UVM testbenches to verify ASIC digital designs from scratch.
• Review and edit target specifications for completeness.
• Develop test plans and specifications for complex SOC blocks.
• Verify complex digital designs using RTL methods (Verilog, SystemVerilog, UVM).
• Collaborate on verification plans and coverage metrics.
• Support DFT, test hooks, and production test planning.

Skills

UVM

SystemVerilog

Verilog

VHDL

RTL design

EDA tools

VCS-MX

Verdi

Questa

UPF

Education

Bachelor's/Master's in Electronic Engineering or Computer Science

Tools

Synopsys VCS-MX

Mentor Questa

Synopsys Formality

Mentor Calibre

Job description

An experienced ASIC Design Verification Engineer takes ownership of the full chip development from architecture definition through to release to production. The right candidate will be someone with high aptitude who is currently hands on verifying complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiation-hardened design, analog/mixed-signal design and EDA, and designing complex RTL.

The candidate is expected to mainly verify circuits, logic, systems, and algorithms using UVM and System Verilog to meet product requirements. The individual will advise the proper method and procedures to be used in the digital system development and determine the best method for verifying the digital system before the complete design is committed to silicon. Candidate must have experience in implementing the proposed method and procedure to design and verify ASIC digital circuits

Essential Duties and Qualification

• s:Development of UVM testbenches to verify ASIC digital designs from scratc
• h.Reviewing and editing target specifications as required for completeness and feasibilit
• y.Developing test plans and specifications for complex design blocks and SOC
• s.Verifying complex digital designs using reusable RTL methods (Verilog, VHDL, System Verilog, UVM
• ).Complex computational architectures and algorithms, such as multi-rate/DSP and µP desig
• n.Modern verification methods, incl. directed/constrained-random stimuli, assertions, TLM and UV
• M.Collaborative creation of comprehensive verification plans and coverage metric
• s.Verifying multi-supply-domain and UPF method
• s.Supporting place & route efforts, incl. P/G and floorplanning, timing and physical constraints, gated CTS, MCMM setups, back-annotation, timing closure, equivalence checkin
• g.Verify the planning, implementing, and analyzing of designs for DFT, test hooks, and scan/ATPG/JTAG/BIST, and supporting production test with ATE patterns (ATPG and functional) and timeset definition
• s.Proficiency with Synopsys EDA, incl. VCS-MX, Verdi, Formality, et
• c.Proficiency with Mentor EDA, incl. Questa, ADMS, Tessen
• t.Modern revision-control tools and best-practices in a collaborative, multi-site design communit
• y.Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scriptin
• g.Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversio

Qualificatio

• ns:Bachelors/master’s in electronic engineering/computer science or equivale
• nt.7+ years of direct industry experience with ASIC and/or SoC desi
• gn.A strong background in RTL based digital IC design using Verilog/SystemVeril
• og.Proven track record of first-pass success
• es.A self-starter with the ability to assume leadership rol
• es.Ability to work well in a diverse team environme
• nt.Willingness to Mentor newer enginee
• rs.Experience with industry standard development tools and methodologi