Senior ASIC/RTL Verification Engineer

TPI Global Solutions; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology solutions provider is seeking an experienced ASIC/RTL Design Engineer for a 12-month contract role. Responsibilities include developing verification tests, debugging failures, and collaborating with engineering teams. The ideal candidate has over 10 years of ASIC design verification experience and is proficient in C/C++, Verilog, and System Verilog. This position is W2 only, located in California.

Qualifications

• 10+ years of ASIC design verification experience.
• Experience with DDR or Memory Controller is a plus.
• Proficient in debugging firmware and RTL code using simulation tools.

Responsibilities

• Develop and maintain tests for functional verification.
• Build and debug directed and random verification tests.
• Provide technical support to other teams.

Skills

C/C++

Verilog

System Verilog

UVM

Python

Perl

TCL

Education

Bachelor's or master's degree in computer engineering/Electrical Engineering

Job description

A leading technology solutions provider is seeking an experienced ASIC/RTL Design Engineer for a 12-month contract role. Responsibilities include developing verification tests, debugging failures, and collaborating with engineering teams. The ideal candidate has over 10 years of ASIC design verification experience and is proficient in C/C++, Verilog, and System Verilog. This position is W2 only, located in California.