ASIC Verification Engineer II — Data Center Silicon

Cisco; Milwaukee (WI); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Annual bonus

Restricted stock units

Paid time off

Job summary

Cisco’s Silicon One team is seeking an ASIC Engineer to verify data center ASICs across simulation, emulation, and bring-up. You will collaborate with verification engineers, designers, and hardware teams to ensure integration and optimal performance of Cisco’s hardware platforms.

You will maintain DV environments, build test benches, develop test plans, and drive coverage closure with emphasis on SystemVerilog, UVM, and scripting.

Qualifications

• Master's degree with 0 years of work experience or Bachelor's with 2 years of work experience in ASIC Engineering, Verification or related field.
• Experience with SystemVerilog and UVM.
• Experience with Perl and/or Python.

Responsibilities

• Maintaining existing DV environments and enhancing them.
• Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks.
• Write test plan, develop test cases, debug regression failures and drive to module verification closure.
• Ensuring complete verification coverage through implementation and review of code and functional coverage.

Skills

SystemVerilog

UVM

Python

Perl

Testbench

Education

Master's in ASIC/Verification

Bachelor's in related field

Tools

Veloce

HAPS

Verilog simulators

Job description

Cisco’s Silicon One team is seeking an ASIC Engineer to verify data center ASICs across simulation, emulation, and bring-up. You will collaborate with verification engineers, designers, and hardware teams to ensure integration and optimal performance of Cisco’s hardware platforms.

You will maintain DV environments, build test benches, develop test plans, and drive coverage closure with emphasis on SystemVerilog, UVM, and scripting.