Senior ASIC Verification & DFT Lead - Onsite San Jose

Experis Technology Group; San Jose (CA); On-site; USD 69,000 - 76,000; Full time

Benefits offered by this job

Medical and Prescription Drug Plans

Dental Plan

Vision Plan

Health Savings Account

401(k) with match

Weekly Pay

Job summary

ManpowerGroup, through its Experis brand, seeks a Senior ASIC Verification Engineer to lead DFT and ASIC verification for next-gen coherent optical products in San Jose. Onsite role with pay range $50-$55 per hour on W-2, focusing on SSN-based DFT architectures and ATPG pattern generation.

The candidate will drive RTL/debug activities, integrate DFT fabrics, and automate verification using Python/Tcl/C++. Strong emphasis on scan insertion, BIST, and post-silicon validation.

Qualifications

• Bachelor’s degree or higher with 8+ years of related experience, or equivalent combination.
• Experience with ASICs, including scan insertion and DFT setup, integration and validation.
• Experience implementing DFT architectures including scan insertion, compression/decompression logic, and memory/logic BIST.
• Strong RTL background to debug DFT-related clocking and integration challenges.
• Proficiency with Verilog/SystemVerilog and solving clock-domain crossing issues.

Responsibilities

• Lead implementation of SSN-based test flow DFT architectures using Siemens Tessent for RTL and gate netlist DFT.
• Generate ATPG test patterns for stuck-at, transition, cell-aware, and path delay fault models; support post-silicon validation.
• Assess RTL and physical design DFT feasibility with Scan Design Rule Check (DRC) tools; ensure DFT readiness.
• Integrate DFT fabrics and IP within subsystems and verify connectivity, behavior, and coverage.
• Develop test scripts and automate processes using Python, Tcl, or C++; run simulations and debug non-timing gate-level models.

Skills

DFT

ATPG

Verilog/SystemVerilog

Python

Tcl

C++

Scan insertion

RTL debugging

Education

Bachelor’s degree in Electrical Engineering or related field

Master’s degree in Electrical Engineering or related field

PhD in Electrical Engineering or related field

Tools

Siemens Tessent

SDF timing

RTL simulation

Job description

ManpowerGroup, through its Experis brand, seeks a Senior ASIC Verification Engineer to lead DFT and ASIC verification for next-gen coherent optical products in San Jose. Onsite role with pay range $50-$55 per hour on W-2, focusing on SSN-based DFT architectures and ATPG pattern generation.

The candidate will drive RTL/debug activities, integrate DFT fabrics, and automate verification using Python/Tcl/C++. Strong emphasis on scan insertion, BIST, and post-silicon validation.