ASIC Engineering Technical Leader

Capgemini; San Jose (CA); On-site; USD 57,000 - 90,000; Part time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Retirement benefits

Job summary

Tundra Technical Solutions in San Jose, CA is seeking an ASIC Engineering Technical Leader (Contract) to drive DFT solutions for next‑gen ASICs used in high‑speed optical products. On‑site, 5 months 21 days contract, immediate start.

You will lead SSN‑based test flows, including scan insertion, compression/decompression, and memory/logic BIST, using Tessent. Strong RTL/Timing skills and scripting in Python/Tcl/C++ are preferred.

Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years, or PhD + 3 years.
• Prior experience with ASICs.
• Prior experience in scan insertion and DFT setup, integration and validation.
• Experience implementing DFT architectures including scan insertion, compression/decompression logic, and memory/logic BIST.

Responsibilities

• Lead SSN-based test flow DFT architectures including scan insertion and memory/logic BIST.
• Generate ATPG patterns for stuck-at, transition, cell-aware and path-delay fault models.
• Drive scan-based diagnosis and post-silicon testing support.
• Evaluate design readiness for RTL and physical design Scan DRC checks.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run simulations and debug non-timing and SDF-back annotated timing.
• Develop test scripts and analyze data using Python, Tcl, or C++.

Skills

Leadership

Problem solving

Mentoring

Education

Bachelor's degree or higher in Electrical/Computer Engineering

Master's degree or PhD preferred

Tools

Siemens Tessent

Verilog/SystemVerilog

Python

Tcl

C++

Job description

ASIC Engineering Technical Leader (Contract)

San Jose, CA, United States (On-site)

Contract (5 months 21 days)

Published 2 days ago

Problem - Solving Skills

EDA tools

We are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with focus in Design-for-Test. In this role, you will be leading development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products.

Key Responsibilities:

Lead implementation of SSN based test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT implementation.

Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models, drive scan-based diagnosis methodology for Silicon failure debug, and provide post-silicon testing and validation support

Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools

Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems

Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations

Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Minimum Qualifications:

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

Prior experience working with ASICs

Prior experience in scan insertion and DFT setup, integration and validation

Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.

Preferred Qualifications:

10+ years of experience working with ASICs

10+ years of experience in scan insertion and DFT setup, integration and validation

3+ years of experience in SSN

Experience driving ASIC DFT execution from concept through tapeout

Experience working with ATE testers and test teams

RTL experience to understand and debugging issues pertaining to DFT

Ability to solve complex problems including clock domain crossings

Familiar with advanced silicon process and technology nodes for high speed and low power consumption

Strong implementation or integration of design blocks using Verilog/System Verilog

The pay range that the employer in good faith reasonably expects to pay for this position is $41.61/hour - $65.01/hour. Our benefits include medical, dental, vision and retirement benefits. Applications will be accepted on an ongoing basis.

Tundra Technical Solutions is among North America’s leading providers of Staffing and Consulting Services. Our success and our clients’ success are built on a foundation of service excellence. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Unincorporated LA County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: client provided property, including hardware (both of which may include data) entrusted to you from theft, loss or damage; return all portable client computer hardware in your possession (including the data contained therein) upon completion of the assignment, and; maintain the confidentiality of client proprietary, confidential, or non-public information. In addition, job duties require access to secure and protected client information technology systems and related data security obligations.