Senior ASIC Verification Architect & Testbench Lead

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity awards

Comprehensive benefits

Job summary

Broadcom in San Jose, CA is seeking an experienced Verification Architect to lead scalable testbenches and drive coverage for Block/Core/SOC designs. You will develop pseudo-random tests, fix regressions, mentor juniors, and document verification strategies. Must have 12+ years in verification, SystemVerilog, UVM/VMM, and full ASIC cycle with tapeout.

Join a team that values rigorous validation, scalable environments, and cross-team collaboration to ensure high-quality silicon products.

Qualifications

• Bachelor's degree in Electrical/Electronics/Equivalent with 12+ years of experience; or Masters degree in Electrical/Electronics/Equivalent with 10+ years of experience
• 10+ years of experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing
• Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification
• Very proficient in SystemVerilog and Verification Methodologies like UVM/VMM
• Good debug skills in analyzing regression failures and understanding of complex designs
• A good understanding of a complex protocol like PCI Express or other multi-layered protocol
• Work with the team and mentor junior engineers

Responsibilities

• Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.
• Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
• Build pseudo-random tests to verify and get to full Functional coverage and bring the Verification to closure
• Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
• Work with other members of the team, guide/mentor junior team members
• Think differently and out-of-the-box to stress the DUT and verify it in an efficient way.
• Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
• Driver Verification quality and Efficiency improvements

Skills

ASIC verification

Test plan development

Regression debugging

Mentor junior engineers

Verification strategy

Education

Bachelor’s degree in Electrical/Electronics/Equivalent

Master’s degree in Electrical/Electronics/Equivalent

Tools

SystemVerilog

UVM

VMM

Job description

Broadcom in San Jose, CA is seeking an experienced Verification Architect to lead scalable testbenches and drive coverage for Block/Core/SOC designs. You will develop pseudo-random tests, fix regressions, mentor juniors, and document verification strategies. Must have 12+ years in verification, SystemVerilog, UVM/VMM, and full ASIC cycle with tapeout.

Join a team that values rigorous validation, scalable environments, and cross-team collaboration to ensure high-quality silicon products.