Senior ASIC Design & Verification Engineer (Onsite SJ)

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA seeks an experienced ASIC Design Verification Engineer to drive architecture, verification, and debugging of high-performance ASICs. You’ll own multiple functional areas, develop reusable code, and participate in chip-level issue resolution.

The role requires strong SystemVerilog experience, Linux, C/C++, and networking knowledge, with opportunities to lead DV methodologies and lab bring-up across platforms.

Qualifications

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 2 years of related experience
• Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools.

Responsibilities

• Drives the definition, architecture and design and verification of high performance ASICs
• Owns complex or multiple functional areas
• Develops reusable code for future projects
• Creates re-usable code
• Debugs at ASIC, SW, HW level
• Leads design and DV work by solving block level issues and participates in chip level issue resolution
• Drives reviews and recognizes areas of architectural concerns
• Defines new verification methodologies
• Helps in lab bring up
• Leads code reviews at platform level
• Identifies, designs and implements power saving solutions

Skills

SystemVerilog

Debugging

Design verification

Methodology

Linux

C/C++

Networking

Education

Bachelor's degree in Electrical Engineering or related field

Advanced degree (MS/PhD) preferred

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco Systems, Inc. in San Jose, CA seeks an experienced ASIC Design Verification Engineer to drive architecture, verification, and debugging of high-performance ASICs. You’ll own multiple functional areas, develop reusable code, and participate in chip-level issue resolution.

The role requires strong SystemVerilog experience, Linux, C/C++, and networking knowledge, with opportunities to lead DV methodologies and lab bring-up across platforms.