Senior ASIC Verification Engineer (SystemVerilog & UVM)

Broadcom Inc.; San Jose (CA); On-site; USD 120,000 - 192,000; Full time

Benefits offered by this job

401(K) with company matching

Employee Stock Purchase Program

Paid vacation and sick leave

Job summary

Broadcom Inc. is looking for a Verification Engineer in San Jose, California. The successful candidate will develop verification plans and build verification environments for advanced ASIC products. Applicants should have substantial experience in verification methodologies and programming skills in Python and C/C++. This position includes a comprehensive benefits package and competitive salary.

Qualifications

• 8+ years of relevant industry experience.
• Strong expertise in RTL verification methodologies.
• Experience with ASIC verification flows.

Responsibilities

• Develop and execute verification plans for IP blocks.
• Build and maintain System Verilog/UVM-based verification environments.
• Collaborate with design, architecture, and verification teams.

Skills

RTL verification methodologies

System Verilog

UVM/OVM

Python

C/C++

Debugging and problem-solving skills

Communication

Teamwork

Education

Bachelor’s degree in Electrical/Electronic Engineering, Computer Science, or related field

Tools

System Verilog

Python

AI-assisted tools

Job description

Broadcom Inc. is looking for a Verification Engineer in San Jose, California. The successful candidate will develop verification plans and build verification environments for advanced ASIC products. Applicants should have substantial experience in verification methodologies and programming skills in Python and C/C++. This position includes a comprehensive benefits package and competitive salary.