Senior ASIC Verification Engineer – IC Design & Tapeouts

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave

Vacation time

Paid Family Leave

Job summary

Broadcom seeks an experienced ASIC verification engineer to join the system-level verification team. You will develop complex verification environments, create comprehensive test plans, and verify high‑performance network switch ASIC/FPGA designs.

This hands-on role spans from testbench architecture to full verification closure, requiring collaboration with system architects, design and verification teams, and a track record of multiple tape-outs.

Qualifications

• 8+ years ASIC design/verification experience with Verilog
• Bachelor's in Engineering
• Strong knowledge of object-oriented programming and modern ASIC verification flows (UVM/SystemVerilog)
• mastery of Verilog for simulation and familiarity with ASIC design flows for deep sub-micron technologies
• Experience with networking protocols (Ethernet, PCIe, routing/switching) is a major plus
• Must have completed multiple ASIC tape-outs from concept to production
• Excellent technical and business English communication

Responsibilities

• Develop complex verification environments and test plans
• Verify high-performance network switch ASIC/FPGA blocks
• Hands-on implementation across all ASIC verification aspects
• Collaborate with system architects, design engineers, and verification teams
• Architect testbenches from initial concept through full production

Skills

Verilog

C/C++

OOP

UVM

SystemVerilog

Networking knowledge

Communication

Education

Bachelor's in Engineering

Tools

Verilog simulators

Job description

Broadcom seeks an experienced ASIC verification engineer to join the system-level verification team. You will develop complex verification environments, create comprehensive test plans, and verify high‑performance network switch ASIC/FPGA designs.

This hands-on role spans from testbench architecture to full verification closure, requiring collaboration with system architects, design and verification teams, and a track record of multiple tape-outs.