Senior ASIC Digital Architect - DDR/PCIe/UCIe Leader

Synopsys, Inc.; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health benefits

Professional development

Retirement plan

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Architect in Austin, TX to define and drive RTL design and verification at chip and block levels. You will lead design plans for high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet, while mentoring engineers and promoting best practices.

The role emphasizes collaboration across teams, advanced methodologies, and ongoing improvements to ensure first-rate digital core performance and reliability in cutting-edge semiconductor solutions.

Qualifications

• Requires BSEE or MSEE with extensive ASIC RTL design experience.
• Deep knowledge of DDR, PCIe, UCIe, Ethernet IO protocols.
• Proficiency with advanced digital design methodologies.

Responsibilities

• Define and develop ASIC RTL design and verification at both chip and block levels.
• Create and execute design plans for complex digital designs, focusing on high-speed IO protocols including DDR, PCIe, CXL, UCIe, and Ethernet technologies.
• Collaborate with cross-functional teams to ensure seamless integration and functionality of designs.
• Utilize advanced design and verification methodologies and tools to achieve high-quality results.
• Mentor engineers and promote best practices, technical excellence, and continuous improvement.
• Communicate with internal and external stakeholders to align goals and deliverables.

Skills

ASIC RTL design

Leadership & mentoring

Strong communication

Problem solving

Education

BSEE or MSEE

Tools

DDR

PCIe

UCIe

Ethernet

Job description

Synopsys, Inc. is seeking an experienced ASIC Digital Architect in Austin, TX to define and drive RTL design and verification at chip and block levels. You will lead design plans for high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet, while mentoring engineers and promoting best practices.

The role emphasizes collaboration across teams, advanced methodologies, and ongoing improvements to ensure first-rate digital core performance and reliability in cutting-edge semiconductor solutions.