Senior Post-Silicon Validation Engineer – Networking ASICs

Jobtailor; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Jobtailor is seeking a senior hardware validation engineer to lead hands-on post-silicon validation for networking ASICs and evaluation platforms in a San Jose lab. You will own early bring-up from first power-on to feature enablement and define validation plans across functionality, performance, and reliability.

You will drive lab readiness, test coverage strategy, and lab automation using Python while overseeing high-speed interfaces and complex signal integrity analyses.

Qualifications

• Bachelor's degree or higher with 6+ years in post-silicon electrical validation or related lab-based silicon debug.
• Experience in electronics, digital logic, signal integrity and power integrity.

Responsibilities

• Lead hands-on post-silicon electrical validation in lab environments for networking ASICs and evaluation platforms.
• Own early-silicon bring-up activities from first power-on through feature enablement.
• Define, execute, and refine detailed hardware validation plans covering functionality, performance, and reliability.
• Drive validation readiness, lab infrastructure setup, and test coverage strategy.
• Lead power-on sequencing, reset strategy validation, clock bring-up, and strap configuration.
• Perform in-depth voltage, current, power integrity, and signal integrity analysis.
• Capture, analyze, and interpret waveforms, eye diagrams, jitter, BER, PDN measurements, power supply stability and noise.

Skills

Post-Silicon Validation

Hardware Bring-Up

Signal Integrity

High-Speed Measurement

Lab Automation

Python

Scripting for Lab Automation

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in related field

PhD in related field

Tools

Oscilloscope

Logic Analyzer

Protocol Analyzer

BERT

VNA

Traffic Generators

Chambers

Chillers

Python

Job description

Jobtailor is seeking a senior hardware validation engineer to lead hands-on post-silicon validation for networking ASICs and evaluation platforms in a San Jose lab. You will own early bring-up from first power-on to feature enablement and define validation plans across functionality, performance, and reliability.

You will drive lab readiness, test coverage strategy, and lab automation using Python while overseeing high-speed interfaces and complex signal integrity analyses.