Senior Physical Design and Timing Engineer

NVIDIA Corporation; Westford (MA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Design Engineer to drive timing for high-frequency DPUs/SoCs across block to full-chip levels. You will optimize constraints, manage ECO-led timing closure, and push RTL-to-GDS2 through front-end and back-end stages.

Ideal candidates have strong STA, ECO, Lean EDA tooling expertise (PrimeTime/Tempus) and scripting with Python, Tcl, and Make. Compensation includes base salary, equity, and benefits.

Qualifications

• BS or MS in Electrical or Computer Engineering with required years of experience.
• Hands-on STA, timing constraints generation and management.
• Experience in ECOs and timing convergence for front-end and back-end flows.

Responsibilities

• Drive physical design and timing of high-frequency DPUs and SoCs.
• Analyze constraints and synthesis parameters to meet perf/area targets.
• Guide RTL to GDS2 flow including ECO implementation and timing convergence.

Skills

STA

Synthesis

Timing convergence

ECOs

LEC

EDA tools

Python

Tcl & Make

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology—and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you'll be doing

• You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level.
• Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.
• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

What we need to see

• Great teammate BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
• Background in logic synthesis and/or logical equivalence checking (LEC).
• Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus).
• Proficiency in Python, Tcl and Make for automation and scripting tasks.

Ways to stand out from the crowd

• Background in domain specific STA and timing convergence, such as CPUs, GPUs or Network processor implementation or SOCs.
• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.
• Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations.
• Experience in methodology and/or flow development as well as automation.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 8, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.