Senior ASIC Synthesis & Timing Lead for AI Accelerators

Positron AI; Austin, Northern (TX, KY); Hybrid; USD 190,000 - 280,000; Full time

Benefits offered by this job

Fully company-paid health insurance

Life and disability coverage

Unlimited PTO

13 paid holidays

Remote-first culture with home office

401(k) with company matching

Equity

Job summary

Positron AI seeks a Senior Mid-End ASIC Engineer to own synthesis, timing convergence, and implementation-ready netlists for AI accelerator chips. You will drive QoR, constraints, and a timing-closure strategy while partnering with RTL, verification, and backend teams.

The role requires hands-on work with Cadence Genus and Design Compiler, and expertise across SDC, MMMC, and scripting (Tcl/Python) on 5nm+ nodes. Remote-first environment with competitive compensation.

Qualifications

• 12+ years of ASIC implementation experience with multiple tapeouts.
• Expert in synthesis methodology and flow development.
• Expert in Cadence Genus and/or Design Compiler.
• Strong SDC expertise for constraint development and MMMC.
• Solid RTL design principles and implementation-friendly coding.
• Hands-on experience with 5nm and below nodes.
• Strong Tcl and Python for automation and flow development.
• Excellent debugging and root-cause analysis skills.

Responsibilities

• Own synthesis methodology across current and future ASIC generations.
• Hands-on synthesis using Cadence Genus and Design Compiler.
• Develop and maintain SDC constraints, clocks, and MMMC envs.
• Drive timing closure strategy, QoR, and constraint development.
• Collaborate with architecture and RTL to mitigate timing risks.
• Lead physical-aware optimization with backend teams.

Skills

ASIC implementation

Cadence Genus

Synopsys Design Compiler

SDC constraints

RTL design

5nm+ process nodes

Tcl scripting

Python scripting

Debugging / root-cause analysis

Tools

Cadence Genus

Synopsys Design Compiler

Job description

Positron AI seeks a Senior Mid-End ASIC Engineer to own synthesis, timing convergence, and implementation-ready netlists for AI accelerator chips. You will drive QoR, constraints, and a timing-closure strategy while partnering with RTL, verification, and backend teams.

The role requires hands-on work with Cadence Genus and Design Compiler, and expertise across SDC, MMMC, and scripting (Tcl/Python) on 5nm+ nodes. Remote-first environment with competitive compensation.