Senior ASIC Designer — AI/Data Center Memory Acceleration

Netpreme; Boston, Northern (MA, KY); Hybrid; USD 180,000 - 280,000; Full time

Benefits offered by this job

Performance bonus

Equity grant

Health, Dental, Vision

401(k) match

Life, Disability, AD&D

Lunch stipend

EV charging & parking

Relocation assistance

Visa sponsorship

Job summary

Netpreme is seeking an experienced Senior ASIC Designer to lead RTL design of IPs, subsystems, and SOCs for memory acceleration in AI/data-center contexts. You will drive microarchitecture specs, reviews, and cross‑functional collaboration across architecture, verification, physical design, firmware, and DFT.

The role requires 5+ years in ASIC/SOC design, strong leadership, and deep RTL expertise. Offices in Boston and Santa Clara support on-site work with relocation options.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5+ years of ASIC/SOC digital design experience.
• Excellent leadership, communication, team building and stakeholder management skills.
• Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
• Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
• Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
• Design and tapeout of any advanced silicon device is highly preferred.

Responsibilities

• As part of the Silicon Design Team, responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.
• Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
• Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
• Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
• Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.

Skills

ASIC/SOC design

RTL coding

Microarchitecture

Synthesis

STA/timing closure

Physical design

Verification methodologies

PPA optimization

Cross-functional leadership

Stakeholder management

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

PhD (preferred) in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog

Job description

Netpreme is seeking an experienced Senior ASIC Designer to lead RTL design of IPs, subsystems, and SOCs for memory acceleration in AI/data-center contexts. You will drive microarchitecture specs, reviews, and cross‑functional collaboration across architecture, verification, physical design, firmware, and DFT.

The role requires 5+ years in ASIC/SOC design, strong leadership, and deep RTL expertise. Offices in Boston and Santa Clara support on-site work with relocation options.