Senior ASIC STA Engineer - Timing & Full-Chip Leadership

Tensordyne

Sunnyvale (CA)

On-site

USD 180,000 - 240,000

Full time

9 days ago

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Job summary

Tensordyne in Sunnyvale, CA seeks an experienced ASIC STA lead to guide and implement frontend physical design timingClosure for multimodal AI inference chips. This hands-on role focus on hierarchical STA, full-chip signoff, and optimization of Genus/Innovus workflows with Cadence/Synopsys tools.

You will collaborate with a global engineering team in a fast-paced startup, mentoring peers, writing SDCs for high-speed interfaces, and driving innovative EDA solutions to meet aggressive performance,

Qualifications

10+ years hands-on ASIC engineering experience with VLSI/SoC workflows.
Deep knowledge of physical design workflows and STA analysis.
Ability to write SDCs for PCIe, SerDes, and multi-clock domain blocks.
Individual contributor tech lead with ownership of full-chip timing closure.
Experience guiding backend design teams on timing issues and ECOs.

Responsibilities

Lead ASIC physical STA design and timing-closure workflow for multimodal AI inference products.
Drive optimization and timing exploration workflows for full-chip STA flow.
Collaborate with ASIC teammates to improve workflows and EDA needs.
Ensure scalable, high-performance systems through robust signoff and timing budgets.
Mentor and support backend teams on clock trees, routing and ECO generation.