STA Engineer

eInfochips (An Arrow Company); San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

401k with matching

Disability insurance

HSA/HRA options

Tuition reimbursement

Job summary

eInfochips, an Arrow company, seeks an experienced ASIC STA engineer to lead timing closure across block, sub-chip, and full-chip levels on-site in San Jose, CA. You will perform timing checks and manage ECO tasks, while contributing to extraction and STA flow development and convergence strategies.

Bachelor's degree required; 8+ years in ASIC STA; 5+ years digital IC design with Synopsys EDA tools; strong problem-solving and communication abilities; proficient in Windows/Linux and MS Office;

Qualifications

• Degree in Electrical Engineering or Computer Engineering
• 8 years of ASIC STA (Static Timing Analysis) experience
• 5 or more years of experience with digital IC design using Synopsys EDA tools
• Strong technical problem-solving skills
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight
• Experience with Siemens Physical Verification tools and methods
• Radiation effects analysis knowledge/experience
• Advanced node and SOI CMOS technology design experience

Responsibilities

• Closing timing at block, sub-chip, and full-chip levels with quality checks (setup, hold, transition, noise) and ECO task management
• Extraction and STA flow development, convergence strategies

Skills

8+ years ASIC STA

Synopsys EDA tools

problem solving

communication

attention to detail

multi-project handling

self-starter

Education

Bachelor's Degree in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Cadence Tempus

Primetime/PTPX/Tweaker

Job description

• Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
• Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.
• Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates
• Synthesis Tools: Synopsys DC/DCG/FC.
• Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.
• Scripting: TCL, Perl, or Python.

This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies

He/She will be using following tools and must posses below experience of tools

• Synopsys Design Compiler
• Cadence Tempus

What We Are Looking For:

• Degree in Electrical Engineering or Computer Engineering
• 8 years of ASIC STA (Static Timing Analysis) experience
• 5 or more years of experience with digital IC design using Synopsys EDA tools
• Strong technical problem-solving skills
• Windows OS and LINUX OS and Microsoft office suite tools proficiency
• Effective and clear communication skills and good ability to work with others
• Work accurately with excellent attention to detail
• Ability to work simultaneously on multiple projects and follow up on responsibilities
• Self-starter who requires minimal oversight
• Experience with Siemens Physical Verification tools and methods
• Radiation effects analysis knowledge/experience
• Advanced node and SOI CMOS technology design experience

What's In It for You:

At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package.

• 401k, With Matching Contributions
• Short-Term/Long-Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Tuition Reimbursement
• And more!

Education:

Bachelor's Degree

Work Arrangement Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location: Complete On-Site at San Jose CA (Day-1 Onsite)

About eInfochips:

eInfochips, an Arrow company (Fortune #133), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow's Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals.

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)