Senior ASIC/SoC Verification Engineer – UVM & Gate-Level Simulation

Amiseq Inc.; United States; On-site; USD 140,000 - 180,000; Full time

Job summary

Amiseq Inc. is seeking an experienced ASIC/SoC Verification Engineer to design and implement robust verification environments using SystemVerilog and UVM. The role focuses on GLS timing, coverage, and regression debugging to ensure design readiness for sign-off.

The ideal candidate has 6–10+ years of hands-on experience, builds UVM testbenches from scratch, and collaborates with design teams to resolve complex issues and validate complex chip designs end-to-end.

Qualifications

• 6–10+ years of ASIC/SoC verification experience.
• Hands-on experience building UVM environments from scratch.
• Expert knowledge of SystemVerilog and UVM.
• Extensive experience with Gate-Level Simulation (GLS) including SDF timing and timing-related debugging.
• Strong knowledge of functional coverage, assertions, regression testing, and waveform analysis.
• Experience with industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Excellent debugging, problem-solving, and root-cause analysis skills.

Responsibilities

• Build UVM-based verification environments from scratch, including testbenches, agents, drivers, monitors, sequences, scoreboards, and coverage models.
• Develop and execute test cases using SystemVerilog and UVM to verify complex ASIC/SoC designs.
• Perform functional verification using directed and constrained-random testing techniques.
• Run Gate-Level Simulations (GLS) and debug timing-related issues, reset problems, initialization failures, and unknown-state (X-propagation) issues.
• Work with SDF timing information to validate the design after synthesis and physical implementation.
• Analyze simulation waveforms, identify root causes of failures, and debug regression issues.
• Track functional coverage, develop assertions, and ensure verification coverage is complete.
• Support verification sign-off and work closely with design and architecture teams to resolve issues.

Skills

SystemVerilog

UVM

GLS/Timing Debugging

Debugging & Troubleshooting

Regression Testing

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

We are looking for an experienced ASIC/SoC Verification Engineer with strong hands-on expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS).

The ideal candidate should be able to build complete verification environments from scratch, verify complex chip designs, identify design issues, and ensure the design is ready for final sign-off.

Key Responsibilities

• Build UVM-based verification environments from scratch, including testbenches, agents, drivers, monitors, sequences, scoreboards, and coverage models.
• Develop and execute test cases using SystemVerilog and UVM to verify complex ASIC/SoC designs.
• Perform functional verification using directed and constrained-random testing techniques.
• Run Gate-Level Simulations (GLS) and debug timing-related issues, reset problems, initialization failures, and unknown-state (X-propagation) issues.
• Work with SDF timing information to validate the design after synthesis and physical implementation.
• Analyze simulation waveforms, identify root causes of failures, and debug regression issues.
• Track functional coverage, develop assertions, and ensure verification coverage is complete.
• Support verification sign-off and work closely with design and architecture teams to resolve issues.

Required Skills & Qualifications

• 6–10+ years of experience in ASIC/SoC Design Verification.
• Strong hands-on experience building complete UVM verification environments from scratch.
• Expert knowledge of SystemVerilog and UVM.
• Extensive practical experience with Gate-Level Simulation (GLS), including SDF annotation and timing-related debugging.
• Strong understanding of functional coverage, assertions, regression testing, and waveform analysis.
• Experience with industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Excellent debugging, problem-solving, and root-cause analysis skills.

Good to Have

• Experience with high-speed protocols such as Ethernet, PCIe, or UCIe.
• Experience verifying complex ASIC/SoC designs through the complete verification lifecycle, from planning to sign-off.

Ideal Candidate

We are looking for someone who has built UVM testbenches from scratch and has strong hands-on GLS debugging experience. Candidates with only general verification experience or limited exposure to Gate-Level Simulation may not be suitable.

Experience Required: 6–10+ years

Core Skills: SystemVerilog, UVM, ASIC/SoC Verification, Gate-Level Simulation (GLS, SDF), Functional Coverage, Assertions, and Debugging.