Senior ASIC/SoC Micro-Architect & RTL Designer (Hybrid)

Platform Recruitment; San Francisco (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

Equity

Generous PTO

Medical/Dental/Vision

401(k) match

Parental leave

Professional development budget

Commute/home-office support

Job summary

Platform Recruitment in the Bay Area seeks a seasoned silicon design engineer to own architecture-to-sign-off for next-generation ASICs/SoCs. Hybrid work with on-site collaboration a few days weekly, remote considered for the right candidate.

You will drive micro-architecture through tapeout, collaborate with verification and physical design teams, and deliver high-performance silicon for AI workloads.

Qualifications

• 5+ years with SystemVerilog, Python, and C/C++ in chip design flows.
• Production-proven micro-architecture and design experience for high‑perf compute.
• Experience driving design from architecture through sign-off with verification partners.

Responsibilities

• Contribute to architecture-to-design methodology spanning blocks to full-chip design.
• Own subsystem or chip-level deliverables from micro-architecture to RTL sign-off.
• Lead reviews on micro-architecture, specs, progress, and timing/area closure.
• Partner with verification, DFT, and physical design to achieve top PPA.

Skills

SystemVerilog

Python

C/C++

Micro-architecture design

Synthesis

DFT

Physical design

Job description

Platform Recruitment in the Bay Area seeks a seasoned silicon design engineer to own architecture-to-sign-off for next-generation ASICs/SoCs. Hybrid work with on-site collaboration a few days weekly, remote considered for the right candidate.

You will drive micro-architecture through tapeout, collaborate with verification and physical design teams, and deliver high-performance silicon for AI workloads.