Senior RTL Design Engineer for LPDDR PHY & ASIC Automation

Synopsys, Inc.; Boxborough (MA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Comprehensive health and wellness benefits

Financial benefits

Job summary

Synopsys, Inc. is seeking an experienced digital design engineer to contribute to LPDDR PHY IP projects that power mobile and AI applications. This role focuses on designing RTL modules, optimizing designs for various targets, and developing automation processes.

Ideal candidates will have extensive ASIC digital design experience, strong Verilog skills, and a Bachelor’s or Master’s in Electrical Engineering. This position offers a comprehensive range of benefits, supporting your health and wellness.

Qualifications

• 10+ years of ASIC digital design experience with RTL ownership in production silicon.
• Expert Verilog proficiency for timing-critical designs.
• Strong Perl scripting skills for design automation.

Responsibilities

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation.
• Optimize designs to meet timing, power, and area targets across multiple process nodes.
• Develop Perl automation for design generation and flow integration.

Skills

ASIC digital design experience

Verilog proficiency

Perl scripting skills

Synthesis and timing analysis

Education

Bachelor's or Master's degree in Electrical Engineering

Job description

Synopsys, Inc. is seeking an experienced digital design engineer to contribute to LPDDR PHY IP projects that power mobile and AI applications. This role focuses on designing RTL modules, optimizing designs for various targets, and developing automation processes.

Ideal candidates will have extensive ASIC digital design experience, strong Verilog skills, and a Bachelor’s or Master’s in Electrical Engineering. This position offers a comprehensive range of benefits, supporting your health and wellness.