Senior Analog & LPDDR PHY Design Manager

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

Advanced Micro Devices, Inc. (AMD) in Santa Clara, CA, seeks a Memory I/O design lead to define and implement high-speed LPDDR PHYs. You will shape circuit architecture, calibrations, and link-performance models, collaborating with Analog, Digital, Firmware and Verification teams to ensure robust, low-power designs.

The ideal candidate brings a proven track record in PHY design and IP development, with strong communication and team leadership skills in a multidisciplinary environment.

Qualifications

• Bachelor's, Master's or Ph.D. in computer engineering/Electrical Engineering.
• Strong/solid knowledge of high-speed IOs and LPDDR PHYs.
• Experience with circuit-architecture and modeling for high-speed circuit design.

Responsibilities

• Manage and contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHYs
• Work closely with Analog Mixed Signal, Digital Design and Firmware to ensure optimal PHY architecture and algorithms implementation
• Manage execution and deliverables across customers and stakeholders
• Develop models for link-level statistical performance simulation of the PHY and apply to design optimization
• Document micro-architecture and algorithms, guiding teams on training and verification of circuits
• Participate in development flows to improve efficiency and quality of execution

Skills

PHY design

Circuit architecture

Modeling

RTL FW debugging

Team management

Signal integrity

Education

Bachelor's/Master's/Ph.D. in Computer or Electrical Engineering

Tools

Matlab/Simulink

Verilog/AMS

Job description

Advanced Micro Devices, Inc. (AMD) in Santa Clara, CA, seeks a Memory I/O design lead to define and implement high-speed LPDDR PHYs. You will shape circuit architecture, calibrations, and link-performance models, collaborating with Analog, Digital, Firmware and Verification teams to ensure robust, low-power designs.

The ideal candidate brings a proven track record in PHY design and IP development, with strong communication and team leadership skills in a multidisciplinary environment.