Senior ASIC Power Engineer

Triple Crown; Sunnyvale (CA); Hybrid; USD 124,000 - 207,000; Full time

Benefits offered by this job

Health Insurance

Dental Insurance

Vision Insurance

401k

Job summary

A leading engineering talent provider in Sunnyvale, CA, is seeking an ASIC Power Engineer to enhance power efficiency in custom ASICs for AR/VR products. The ideal candidate will have over 10 years of experience in ASIC Power or Physical Design engineering, performing in-depth power analysis and optimization. Responsibilities include RTL-level analysis and ASIC flow debugging. The position offers hybrid work, with comprehensive benefits including health insurance and a 401k plan.

Qualifications

• 10+ years of experience as an ASIC Power engineer or Physical Design engineer.
• Experience in power analysis and optimization for custom ASICs.
• Familiarity with machine learning-related workloads.

Responsibilities

• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis.
• Run, debug and analyze reports of ASIC flows.
• Documentation and clear communication.
• Implement blocks at RTL and UPF.
• Document and communicate clearly.

Skills

ASIC flows

Synthesis

Power

Timing

Scripting

Tools

Fusion compiler

Job description

Job Overview

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

Job Type: Contract

Duration: 6-24+ Months

Location: Hybrid, onsite in Sunnyvale, CA

Requirement: 10+ years of experience as an ASIC Power engineer or Physical Design engineer

We are seeking an experienced ASIC Power Engineer to perform power analysis and optimization for custom ASICs used in AR/VR products. This role focuses on improving power efficiency across complex SoC designs, with exposure to Machine Learning–related workloads and close collaboration with architecture, RTL, and physical design teams.

Responsibilities

• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis.
• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction.
• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF.
• Documentation and clear communication (ability to document and communicate clearly).

Skills

• ASIC flows
• Synthesis
• Power
• Timing
• Scripting

Benefits

• Health, Dental and Vision Insurance
• 401k

Seniority level: Mid-Senior level

Industry: Semiconductor Manufacturing