ASIC Engineer, Power

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta is seeking an ASIC Engineer specializing in power to join the EDA Infrastructure team in Sunnyvale. You will develop and maintain power analysis and optimization flows to help silicon engineers model, estimate, and reduce power consumption in custom ASIC designs.

You will define power methodology, collaborate with RTL and physical design teams, and drive power closure across multiple tape-outs while evaluating new EDA tools and automating workflows.

Qualifications

• Bachelor's degree in CS/CE or related field.
• 6+ years in ASIC design or physical design with power focus.
• Experience building EDA power analysis flows (PrimePower/Voltus).
• Experience with UPF/CPF in RTL-to-GDSII.
• Scripting in Python, Tcl, or shell to automate flows.
• Collaborate across RTL, physical design, and verification.

Responsibilities

• Develop and maintain power analysis flows including dynamic and static power estimation.
• Define and implement power methodology guidelines for RTL, synthesis, and physical design.
• Collaborate with RTL, physical design, and verification to resolve power hotspots.
• Build and optimize EDA automation scripts to improve power signoff turnaround.
• Evaluate and integrate EDA tools into power analysis flow.
• Develop power intent specs using UPF/CPF across design stages.
• Establish power budgets and track metrics across milestones.
• Drive continuous improvement of power closure across tape-outs.
• Provide technical guidance on power analysis best practices.

Skills

Power analysis

Power optimization

Python scripting

Cross-functional collaboration

Communication skills

Education

Bachelor's degree in CS/CE or related field

Tools

Synopsys PrimePower

Cadence Voltus

UPF/CPF

Job description

Summary:

Meta is building custom silicon to power the infrastructure that underlies its family of products and services. As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and maintain power analysis and optimization flows that enable silicon engineers across the organization to accurately model, estimate, and reduce power consumption in custom ASIC designs. In this role, you will work at the intersection of EDA tooling, physical design, and power methodology, helping to define the infrastructure that shapes how Meta's next-generation chips are designed and verified.

Required Skills:

ASIC Engineer, Power Responsibilities:

1. Develop and maintain power analysis flows including dynamic and static power estimation, vectorless analysis, and power intent verification using industry-standard EDA tools

2. Define and implement power methodology guidelines for RTL, synthesis, and physical design stages of the ASIC development flow

3. Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs

4. Build and optimize EDA infrastructure scripts and automation frameworks to improve power signoff accuracy and turnaround time

5. Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow, providing technical assessments and recommendations

6. Develop power intent specifications using UPF or CPF and ensure consistent application across design and implementation stages

7. Establish power budgets and track power metrics across design milestones, communicating results and risks to cross-functional stakeholders

8. Drive continuous improvement of power closure methodologies by analyzing results across multiple tape-outs and identifying systemic opportunities

9. Provide technical guidance to other engineers on power analysis best practices, flow usage, and debug techniques

10. Partner with EDA tool vendors to evaluate new capabilities and influence tool roadmaps to meet Meta silicon design requirements

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. 6+ years of experience in ASIC design or physical design with a focus on power analysis, power optimization, or power signoff

3. Experience developing or maintaining EDA flows for power analysis using tools such as Synopsys PrimePower, Cadence Voltus, or equivalent

4. Experience with power intent specification languages such as UPF or CPF and their application across RTL-to-GDSII flows

5. Experience scripting in Python, Tcl, or shell to build and automate EDA infrastructure workflows

6. Experience collaborating across RTL design, physical design, and verification disciplines to drive power closure on complex ASIC designs

Preferred Qualifications:

Preferred Qualifications:

1. Experience evaluating and qualifying new EDA tools or methodologies in a production silicon environment

2. Familiarity with custom or semi-custom design flows for high-performance computing or data center silicon

3. Experience with low-power design techniques including clock gating, power gating, multi-voltage domain design, and dynamic voltage and frequency scaling

4. Background in developing internal EDA infrastructure tooling or flow automation at scale across multiple concurrent design projects

Public Compensation:

$146,000/year to $209,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affiliation Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].