Senior Silicon Power Engineer — Automation & Tapeouts

Google LLC; Mountain View (CA); On-site; USD 217,000 - 236,000; Full time

Job summary

Google DeepMind in Mountain View seeks a Silicon Engineer, Power Analysis to design and optimize power for production chips. You will architect power solutions, drive RTL power analysis, and integrate power flows across SoC teams to meet performance and efficiency goals.

Required: 7+ years in ASIC power analysis, tape-outs, Verilog, and industry EDA tools (PowerArtist, PrimeTime, Innovus, etc.), plus scripting in Perl or Tcl. Master’s or PhD preferred; strong collaboration skills a must.

Qualifications

• 7+ years in ASIC power analysis for production chips.
• Experience with tape-outs and external vendors.
• Proficient in Verilog and major EDA tools.
• Scripting in Perl and Tcl for automation.

Responsibilities

• Architect advanced power solutions and budgets for blocks and full chips.
• Lead automation and integration of power analysis processes into the flow.
• Build and integrate software components for power analysis and optimization.
• Partner with cross-functional teams to drive power management from SoC design to sign-off.

Skills

Power analysis

ASIC tape-out

Verilog

EDA tools

Perl scripting

Tcl scripting

Collaboration with foundries

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

PowerArtist

PrimeTime

PrimeTime-PX

Cadence Innovus

Synopsys Fusion Compiler

PP-RTLA

Job description

Google DeepMind in Mountain View seeks a Silicon Engineer, Power Analysis to design and optimize power for production chips. You will architect power solutions, drive RTL power analysis, and integrate power flows across SoC teams to meet performance and efficiency goals.

Required: 7+ years in ASIC power analysis, tape-outs, Verilog, and industry EDA tools (PowerArtist, PrimeTime, Innovus, etc.), plus scripting in Perl or Tcl. Master’s or PhD preferred; strong collaboration skills a must.