Senior ASIC Power Delivery Engineer for AI Hardware/TPU

Anysilicon; Sunnyvale (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Google is hiring a Senior Power Design Engineer in Sunnyvale to drive the power delivery strategy for AI/ML hardware accelerators. You will lead power grid architectures, analyze power delivery across advanced processes, and collaborate with design teams to ensure robust power integrity for TPU technology.

The role emphasizes ownership of power grid design, through-silicon via optimization, and alignment with project milestones to enable scalable, high-density power delivery for cutting-edge

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of technical experience in physical design disciplines involving power delivery and advanced process technology nodes.
• Experience with power grid integrity, including budgeting, analysis, verification, and signoff.
• Familiarity with place and route tools, electromigration and IR drop tools, and design rule check tools.

Responsibilities

• Drive early process and metal stack analysis to influence power architecture.
• Deliver power grid designs for all power domains, ensuring they meet power density and integration requirements.
• Optimize through-silicon via and power grid co-design on 3D stacked dies, focusing on design rule check cleanliness and electromigration.
• Collaborate with various design teams to co-optimize designs and accommodate top-level routes.
• Stabilize and finalize power grid designs in alignment with project milestones.

Skills

Power delivery

Grid design

Collaboration

Problem solving

Communication

Education

Bachelor's degree in Electrical / Computer Engineering or related

Master's or PhD in a relevant field (preferred)

Tools

Place and Route Tools

IR drop tools

Electromigration tools

Design rule check tools

Job description

Google is hiring a Senior Power Design Engineer in Sunnyvale to drive the power delivery strategy for AI/ML hardware accelerators. You will lead power grid architectures, analyze power delivery across advanced processes, and collaborate with design teams to ensure robust power integrity for TPU technology.

The role emphasizes ownership of power grid design, through-silicon via optimization, and alignment with project milestones to enable scalable, high-density power delivery for cutting-edge