Power-Efficient AI Accelerator ASIC Engineer

Anysilicon; Sunnyvale (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Google's AI and Infrastructure team in Sunnyvale is seeking an experienced ASIC Design Engineer to advance TPU technology and power-efficient silicon design for AI/ML workloads.

You will model and drive power optimization, define low-power methodologies, and collaborate with software and system teams to implement power-management architectures that meet stringent power and performance goals.

Qualifications

• Bachelor's degree or equivalent in Electrical/Computer Engineering or Computer Science.
• 8 years of experience in silicon design or architecture.
• Experience with power design, modeling or reduction methods.

Responsibilities

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power designs.
• Collaborate with cross-functional software and system teams on power management architectures.

Skills

Power modeling

Power optimization

Low-power design

DVFS

Open-ended problem solving

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE/CS (preferred)

Job description

Google's AI and Infrastructure team in Sunnyvale is seeking an experienced ASIC Design Engineer to advance TPU technology and power-efficient silicon design for AI/ML workloads.

You will model and drive power optimization, define low-power methodologies, and collaborate with software and system teams to implement power-management architectures that meet stringent power and performance goals.