Senior Physical Design Engineer - DSP & PPA Optimization

Qualcomm; Austin (TX); On-site; USD 164,000 - 246,000; Full time

Job summary

Qualcomm is seeking an experienced ASIC Design Engineer to update physical implementation flows and drive the development of design techniques. This role requires a Bachelor's degree in Science, Engineering, or a related field, along with over 12 years of experience in ASIC Physical design.

The compensation package includes a salary range of $164,000.00 - $246,000.00, along with additional benefits like an annual discretionary bonus program.

Qualifications

• 12+ years ASIC Physical design, Synthesis or related work experience.
• Strong proficiency in P&R, timing analysis, CAD tools (e.g., Synopsys FC/DC, ICC2, Cadence Genus, Innovus).
• Very good understanding of logic optimization for high-speed design.

Responsibilities

• Update physical implementation flows for optimum PPA.
• Drive development of semi-custom design techniques.
• Use tools like Fusion Compiler to design complex blocks.

Skills

ASIC Physical design

Synthesis

P&R

timing analysis

CAD tools

architecture and design tools

scripting tools

programming languages

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering

Tools

Synopsys FC/DC

ICC2

Cadence Genus

Innovus

Fusion Compiler

Job description

Qualcomm is seeking an experienced ASIC Design Engineer to update physical implementation flows and drive the development of design techniques. This role requires a Bachelor's degree in Science, Engineering, or a related field, along with over 12 years of experience in ASIC Physical design.

The compensation package includes a salary range of $164,000.00 - $246,000.00, along with additional benefits like an annual discretionary bonus program.