ASIC Physical Design Engineer

Cisco; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco's Common Hardware Group seeks a Physical Design Engineer to drive RTL-to-GDSII implementation across advanced nodes, delivering high-performance networking chips. You will optimize floor planning, timing, and power distribution while collaborating with RTL, DFT, and EDA teams.

The role emphasizes hands-on physical design, timing closure, and tool-driven flow improvements across multi-node projects, with opportunities to shape industry-leading silicon.

Qualifications

• Bachelors degree in Electrical Engineering with 5+ years of related experience, or Masters with 2+ years, or PhD with 0+ years.
• Hands-on ASIC physical design and implementation experience.
• Experience with hierarchical floorplanning, clock/power distribution, global signal/I/O planning, and convergence.
• Experience with designs >100M gates in advanced nodes (16nm–2nm).

Responsibilities

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define hierarchical floor planning, place & route, clock and power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts in STA tools.
• Implement and manage timing ECO strategies using Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps; recommend tool/flow/methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design efficiency.
• Evaluate new timing methodologies; provide debugging solutions.
• Drive methodology alignment across projects.

Skills

asic physical design

floorplanning

timing convergence

static timing analysis

rtl-to-gdsii

power integrity

scripting

place & route

tool fluency

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys FC

Cadence Genus

Synopsys Formality

PrimeTime-DMSA

Cadence LEC

Mentor Calibre

PrimeTime

Voltus/Redhawk

Job description

The application window is expected to close on: 10/08/2026 Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco's core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One-the industry's only unified silicon architecture spanning top-of-rack switches to web-scale data centers-you'll help shape Cisco's groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

Your Impact

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications

• Bachelors degree in Electrical Engineering+ 5 years of related experience, or Masters degree in Electrical Engineering+ 2 years of related experience, or PhD in Electrical Engineering 0+ years of related experience.
• Hands-on experience in ASIC physical design and implementation.
• Experience working with hierarchical floorplanning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.
• Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).

Preferred Qualifications

• Experience with Scripting using languages such as TCL, Python and efficient use of AI tools.
• Place & Route experience using tools such as Cadence Innovus or Synopsys FC.
• Synthesis experience including Cadence Genus/Synopsys FC.
• Formal Verification experience using tools such as Synopsys Formality or Cadence LEC
• Experience with Static Timing Analysis including tools such as PrimeTime-DMSA.
• Experience with Power Integrity including tools such as Apache Redhawk/Voltus
• Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued e