Senior Digital ASIC Physical Design Engineer (Relocation)

Keysight Technologies; Colorado Springs (CO); On-site; USD 142,000 - 236,000; Full time

Benefits offered by this job

Medical, dental and vision

Health Savings Account

Flexible Spending Accounts

Life, Accident, Disability insurance

401(k) Plan

Flexible Time Off

Paid Holidays

Paid Family Leave

Tuition Reimbursement

Employee Stock Purchase Plan

Restricted Stock Units

Job summary

Keysight Technologies in Colorado Springs seeks an experienced Physical Design R&D engineer responsible for the physical design and tape release of digital and mixed signal ASICs. You will lead module and SoC implementation from RTL to GDS, addressing timing, power, and sign-off across cross-functional teams.

The role requires strong industry tapeout experience, leadership, and collaboration with foundries and vendors.

Qualifications

• Industry tapeout experience.
• Desire to identify and debug problems.
• Experience with ASIC Design, DSP, digital architectures/systems, and verification of large and mixed signal ASIC designs.
• Leadership skills to drive teams and partners toward execution.

Responsibilities

• Participate in full ASIC design activities: definition, architectures, digital logic, IP validation and synthesis.
• Floor planning, PNR, timing closure, STA, formal verification, low power design, clock distribution, EMIR analysis, physical verification.
• Close sign-off checks and interface with foundries; deliver GDS.
• Collaborate with cross-functional teams to guide architecture with physical design constraints.
• Develop tool flows and drive vendors to milestones.

Skills

Leadership skills

Teamwork and communication

Problem solving and debugging

Multi-tasking and project management

Object-oriented programming

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Innovus

Tempus

Voltus

Genus

Job description

Keysight Technologies in Colorado Springs seeks an experienced Physical Design R&D engineer responsible for the physical design and tape release of digital and mixed signal ASICs. You will lead module and SoC implementation from RTL to GDS, addressing timing, power, and sign-off across cross-functional teams.

The role requires strong industry tapeout experience, leadership, and collaboration with foundries and vendors.