Senior ASIC Physical Design Engineer – RTL to GDSII

Ralliant; Boulder (CO); On-site; USD 148,900 - 276,500; Full time

Job summary

Tektronix is seeking an experienced ASIC Physical Design Engineer to join one of its design centers in Louisville, CO or Beaverton, Oregon. You will drive floorplanning, placement, clock-tree synthesis, routing, and timing closure for SOCs.

Collaborate with RTL, verification, DFT, and packaging teams to deliver tapeout-ready designs. Strong scripting skills and Cadence/Synopsys/Siemens tools are required.

Qualifications

• BS in Electrical Engineering or equivalent experience.
• 5+ years of hands-on ASIC physical design from RTL to GDS.
• Experience with RTL-to-GDSII flows and congestion/timing resolution.
• Familiarity with DRC, LVS, extraction, and timing closure.
• Proficiency with Tcl, Python, or shell scripting for flows.

Responsibilities

• Execute ASIC digital physical design from RTL to GDSII.
• Drive place-and-route and floorplanning with timing closure.
• Perform static timing analysis across modes and corners.
• Support signoff activities: DRC, LVS, extraction and signoff checks.
• Collaborate with RTL, verification, DFT, analog, packaging teams.
• Develop scripts and flows to improve design methodology.

Skills

RTL-to-GDSII flow

Floorplanning

Place-and-route

Clock tree synthesis

Static timing analysis

DRC/LVS/signoff

Scripting (Tcl/Python)

Education

BS in Electrical Engineering

MS/PhD in Electrical Engineering

Tools

Cadence

Synopsys

Siemens EDA

Job description

Tektronix is seeking an experienced ASIC Physical Design Engineer to join one of its design centers in Louisville, CO or Beaverton, Oregon. You will drive floorplanning, placement, clock-tree synthesis, routing, and timing closure for SOCs.

Collaborate with RTL, verification, DFT, and packaging teams to deliver tapeout-ready designs. Strong scripting skills and Cadence/Synopsys/Siemens tools are required.