Physical Design – Senior Engineer

Thundersoft; Santa Clara (CA); Vor Ort; USD 120.000 - 190.000; Vollzeit

Zusammenfassung

Thundersoft is seeking highly motivated Physical Design Engineers across multiple career levels to join our ASIC implementation team in Santa Clara, CA. You will contribute to the development and execution of advanced physical design methodologies for complex SoCs and IP blocks, working with architecture, RTL, DFT, verification, CAD, and product engineering teams.

The role involves floorplanning, power planning, place-and-route, clock tree synthesis, timing closure, SI analysis, physical

Qualifikationen

• Bachelor's degree with 4+ years ASIC design/verification/validation experience
• Master's degree with 3+ years ASIC design/verification/validation experience
• PhD with 2+ years ASIC design/verification/validation experience
• Experience with digital ASIC physical implementation methodologies
• Understanding of power, performance, area, timing, and physical design tradeoffs
• Experience in Linux/Unix environments
• Proficient in Python, Tcl, Perl, Shell or similar scripting languages
• Strong analytical, problem-solving, and debugging skills
• Successful project execution

Aufgaben

• Floorplanning, power planning, place and route, CTS, routing, timing closure, SI analysis, physical verification, ECO implementation and signoff
• Collaborate with architecture, RTL, DFT, verification, CAD and product engineering teams through tapeout
• Use Cadence Innovus and Synopsys Fusion Compiler for physical design and optimization
• Support advanced SoC programs including GPU, AI, Compute, Connectivity, DDR, Audio and other next-gen technologies
• Ensure timing closure and design signoff across multi-project environments

Kenntnisse

ASIC design

Digital ASIC

PPA tradeoffs

Linux/Unix

Python

Tcl

Shell scripting

Problem solving

Debugging

Ausbildung

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

Jobbeschreibung

Locations - Santa Clara CA/ Austin TX/ San Diego CA

We are seeking highly motivated Physical Design Engineers across multiple career levels to

join our growing ASIC implementation team. In this role, you will contribute to the

development and execution of advanced physical design methodologies for complex, high

performance, low-power SoCs and IP blocks.

You will work closely with architecture, RTL, DFT, verification, CAD, and product

engineering teams to implement and deliver industry leading designs from synthesis

through final tapeout.

The ideal candidate possesses strong technical expertise in physical implementation,

Depending on experience and demonstrated technical leadership, candidates may be

considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer

Physical Design responsibilities include floorplanning, power planning, place and route,

clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO

implementation, and design signoff activities.

The role supports Qualcomm's advanced SoC and core design programs across GPU,

Multimedia, AI, Compute, Connectivity, Modem, DDR, Audio, and other next-generation

technologies.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• successful project execution.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of power, performance, area, timing, and physical design tradeoffs.
• Experience working in Linux/Unix environments.
• Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Preferred Qualifications

• Experience with complete Physical Design Flow from synthesis through tapeout.
• Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure
• Experience using Cadence Innovus and/or Synopsys Fusion Compiler.
• Static Timing Analysis and timing closure experience using Synopsys PrimeTime.
• Knowledge of MMMC implementation methodologies and advanced-node design closure.
• Experience with DFT-aware implementation and functional timing constraints.
• Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification.
• Experience with low-power implementation techniques, UPF methodologies, and power domain analysis.
• Strong communication, collaboration, and technical leadership capabilities.