Senior ASIC/SOC Physical Design Engineer

MatX; Mountain View (CA); On-site; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO

12 company holidays

Up to 3 weeks remote work

Health insurance

Dental and Vision

Life insurance

HSA and FSA

Professional development budget

Team meals

Commuter benefits

MatX extras

Cell & Internet reimbursement

Mental wellbeing

Parental leave

AI resources

Job summary

MatX is seeking silicon physical design engineers to develop high-performance, energy-efficient silicon for GenAI products in Mountain View, CA. You will drive PD across blocks, subsystems, and full-chip scope from RTL to GDSII, owning schedules and sign-offs.

The role requires 8+ years in ASIC PD, strong collaboration with Design/DFT teams, and proficiency in Perl, Python, and TCL. Competitive compensation and comprehensive benefits offered.

Qualifications

• Bachelor of Science in Electrical Engineering required.
• 8+ years of ASIC Physical Design experience.
• Strong interpersonal and communication skills.
• Expertise in PD construction and sign-off from RTL to silicon.

Responsibilities

• Contribute to scalable Physical Design methodologies across blocks, subsystems, and full chip.
• Own subsystems or full-chip PD deliverables including partitioning, floorplanning, synthesis, place & route, clocking, sign-off.

Skills

Perl

Python

TCL

ASIC PD

Education

Bachelor of Science in Electrical Engineering

Job description

MatX is seeking silicon physical design engineers to develop high-performance, energy-efficient silicon for GenAI products in Mountain View, CA. You will drive PD across blocks, subsystems, and full-chip scope from RTL to GDSII, owning schedules and sign-offs.

The role requires 8+ years in ASIC PD, strong collaboration with Design/DFT teams, and proficiency in Perl, Python, and TCL. Competitive compensation and comprehensive benefits offered.