Senior ASIC Performance Modeling & Architecture Engineer

Meta; Harrisburg (Dauphin County); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions for Meta's AI and data center workloads. As an ASIC Engineer specializing in performance and modeling, you will define the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs designed for Meta's infrastructure.

You will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture, design, and software teams.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in ASIC design, silicon engineering, or a related technical field.
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools.
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems.
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon.
• Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams.
• Experience with assembly programming languages, and compiler technologies.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including cycle-accurate and transaction-level environments.
• Drive microarchitectural exploration across compute, memory, interconnect, and I/O domains.
• Develop and validate pre-silicon performance models predicting post-silicon behavior for data center workloads.
• Develop workloads and kernels for ML training and inference.
• Establish performance analysis methodologies, benchmarking, and bottleneck identification across the ASIC pipeline.
• Collaborate with architecture, RTL, and physical design teams to translate requirements into microarchitectural specs.
• Partner with software and systems teams to co-optimize workloads against silicon performance.
• Lead technical reviews and communicate results to leadership.
• Define future performance modeling infrastructure roadmaps and tooling.
• Mentor engineers on performance modeling and microarchitectural analysis.
• Perform root-cause analysis to resolve gaps between modeled and measured silicon behavior.

Skills

C++

Python

SystemC

Performance modeling

Microarchitectural analysis

Cycle-accurate modeling

Pre-silicon simulation

Data center workloads

Education

Bachelor's degree in Computer Science or related field

Equivalent practical experience

Tools

SystemVerilog

VHDL

Simulation frameworks

Job description

Meta's Silicon Engineering organization is building custom silicon solutions for Meta's AI and data center workloads. As an ASIC Engineer specializing in performance and modeling, you will define the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration for custom ASICs designed for Meta's infrastructure.

You will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture, design, and software teams.