Senior ASIC Performance Modeling Architect

Meta; Honolulu (HI); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is seeking an experienced ASIC Engineer specializing in performance and modeling to define and drive architectural performance analysis for custom silicon powering Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level models, validate pre-silicon predictions, and collaborate with architecture, RTL, and software teams to ensure throughput and efficiency targets are met at scale.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 8+ years of experience in ASIC design, silicon engineering, or related field.
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including cycle-accurate and transaction-level simulation environments.
• Drive microarchitectural exploration and trade-off analysis across compute, memory, interconnect, and I/O domains.
• Develop and validate pre-silicon performance models that predict post-silicon behavior for data center workloads.
• Develop low-level workloads and kernels for machine learning training and inference applications.
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques.
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into microarchitectural specs.
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics.

Skills

C++

Python

SystemC

Performance modeling

Microarchitectural analysis

RTL collaboration

Automation scripting

Team leadership

Education

Bachelor's degree in CS/CE or equivalent

Tools

SystemVerilog

Simulation environments

Job description

Meta is seeking an experienced ASIC Engineer specializing in performance and modeling to define and drive architectural performance analysis for custom silicon powering Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level models, validate pre-silicon predictions, and collaborate with architecture, RTL, and software teams to ensure throughput and efficiency targets are met at scale.