ASIC Performance Architect for Hyperscale AI

Meta; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Meta's Silicon Engineering organization is seeking an ASIC Engineer specializing in architecture, performance, and modeling. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level simulations, create C++ models of AI chip IPs, and collaborate with architecture, RTL, and software teams to meet throughput and latency targets

Qualifications

• Bachelor's degree completed before joining Meta
• Master's or PhD completed before joining Meta
• Proficiency in C++ and Python for development of simulation models
• Experience in ASIC performance modeling or pre-silicon simulation
• Experience with data center, AI accelerator, or HPC workloads on custom silicon
• Experience building cycle-accurate or transaction-level models using C++ and SystemC
• Experience with microarchitectural specifications and cross-functional alignment
• Experience with Python-based automation for simulation orchestration

Responsibilities

• Drive microarchitectural exploration across compute, memory, interconnect and I/O to inform silicon architecture decisions
• Define and own the performance modeling strategy for custom ASICs, including cycle-accurate and transaction-level simulations
• Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration
• Develop low-level workloads and kernels for ML training and inference
• Establish performance analysis methodologies, benchmarks, and bottleneck identification techniques
• Collaborate with architecture, RTL, and physical design teams to translate requirements into specifications
• Partner with software teams to optimize workloads against silicon performance
• Lead technical reviews and communicate results to engineering leadership
• Define long-term performance modeling roadmaps and tooling investments
• Mentor engineers on performance modeling and microarchitectural analysis techniques
• Identify and resolve performance gaps between modeled and actual silicon through root-cause analysis

Skills

C++

Python

SystemC

Microarchitectural analysis

Performance modeling

Pre-silicon simulation

Education

Bachelor's degree in CS/CE

Master's or PhD in CS/CE/EE

Tools

CUDA

SystemVerilog

Job description

Meta's Silicon Engineering organization is seeking an ASIC Engineer specializing in architecture, performance, and modeling. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's AI and data center workloads.

You will develop cycle-accurate and transaction-level simulations, create C++ models of AI chip IPs, and collaborate with architecture, RTL, and software teams to meet throughput and latency targets