ASIC Engineer, Performance Architecture and Modeling

Meta; Sunnyvale (CA); Hybrid; USD 190,000 - 240,000; Full time

Job summary

Meta's Silicon Engineering organization in Sunnyvale, CA is seeking an ASIC Engineer specializing in architecture, performance and modeling. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.

Collaborate with architecture, RTL, and software teams to translate performance goals into implementable microarchitectural specifications, develop C++ models of AI IPs, and create workloads for ML

Qualifications

• Experience in pre-silicon modeling and performance analysis.
• Strong software development skills in C++.
• Ability to collaborate with architecture, RTL, and software teams.

Responsibilities

• Drive microarchitectural exploration across compute, memory, interconnect, and I/O.
• Define and own performance modeling strategy for custom infrastructure ASICs.
• Develop and maintain C++ models of AI chip IPs and subsystems.
• Develop workloads and kernels for ML training and inference.
• Collaborate with RTL, design, and physical teams to meet performance targets.

Skills

C++ modeling

Performance analysis

Microarchitecture

Workload development

Collaboration

Tools

Cycle-accurate simulators

Emulation tools

Job description

# ASIC Engineer, Performance Architecture and ModelingSunnyvale, CA+2 locationsHardware+ 2 moreApply nowMeta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.---## ASIC Engineer, Performance Architecture and Modeling Responsibilities* Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions* Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments* Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development* Develop low-level workloads and kernels for machine learning training and inference applications* Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline* Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications* Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics