Hyperscale ASIC Performance Architect & Modeling Lead

Meta; Richmond (VA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.

The role requires 8+ years in ASIC design and 5+ years in performance modeling, with C++ and Python proficiency. Collaboration with architecture, RTL, and software teams is essential to meet throughput, latency, and

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in ASIC design, silicon engineering, or a related technical field.
• 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools.
• Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnects.
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon.
• Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams.
• Experience with assembly programming languages, and compiler technologies.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments.
• Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions.
• Develop and validate pre-silicon performance models that accurately predict post-silicon behavior for data center workloads.
• Develop low-level workloads and kernels for machine learning training and inference applications.
• Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline.
• Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications.
• Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics.
• Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership.
• Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments.
• Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices.
• Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration.

Education

Bachelor's degree in CS/CE or related technical field

Tools

C++

Python

SystemC

SystemVerilog

VHDL

Assembler

Job description

Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.

The role requires 8+ years in ASIC design and 5+ years in performance modeling, with C++ and Python proficiency. Collaboration with architecture, RTL, and software teams is essential to meet throughput, latency, and